To prototype a system it is convenient to have a processor on-chip running at its normal speed, and the logic which is ultimately to be integrated onto the chip as off-chip logic for prototyping purposes, said off-chip logic being for example in the form of an FPGA or an emulator.
Currently, this involves either bonding out the processor core so that its signals are available off-chip, or using one of the existing off-chip communication ports which are already provided on the chip on which the processor is situated. Such ports are generally serial ports or reduced pin out ports such as debug ports, and in any event are not provided as dedicated ports for prototyping but have some already existing function.
In a situation where the processor core is bonded out, there are a number of problems. In the first place, bonding out of a processor's on-chip interfaces uses a lot of pins. The processor has to be run at reduced speed in order for the bond out interface to function reliably. The limitation on the use of pins means that it is difficult to support platform prototyping where some resources are integrated on-chip and some are not.
Where an existing off-chip communication port is used, there are also difficulties. Many such ports require software assistance to function. This software is not required in the integrated system which is under prototype, which means that the prototype software and the final software will have to be different. In effect, the final software cannot run on the prototype and therefore any testing of the prototype cannot completely match the final product.
Where interrupts or power down requests need to be made, these have to be supplied via the off-chip communication port. This means that software assistance is required at the port to allow the prototype to share existing system resources in order to raise interrupts to a core or receive notification of a request to enter a low power mode.